1. Field of Invention
The present invention relates to the field of circuit design technology of a power adapter. More particularly, the present invention relates to a power factor correction (PFC) circuit in which a power adapter can improve operation efficiency under low voltage input and full-load output conditions.
2. Description of Related Art
A power adapter is used as power supply equipment for an electronic product in many fields, such as in the defense industry, the area of science and research, industry control, communications, electrical power, LED lighting and the instrumentation. With the continuous improvement of power adapters, increased attention is being given to the operation efficiency of power adapters under low voltage input and full-load output conditions. However, with the increasing usage of high-frequency power adapters, the switching loss of a power component of such a power adapter increases along with the increase in frequency. Consequently, significant research and development is being conducted with respect to ensuring that operation frequency is not reduced due to switching loss.
In the prior art, a common solution is that in which a bridgeless PFC topology circuit is used to improve the efficiency of the adapter. However, such a topology circuit frequently causes large common mode noise. Furthermore, a totem-pole bridgeless PFC topology circuit may also be used, in which an output capacitor is clamped to the input voltage so as to reduce the common mode noise. However, in such a topology circuit, two serially connected slow-recovery diodes are used, so that in the operation process of the adapter the current always flows through one of the two slow-recovery diodes. Furthermore, under low voltage input and full-load output conditions, the current is large, so is the entire PFC topology circuit the on-state loss of the slow-recovery diode, which limits further efficiency improvement of the adapter.
In view of this, many in the industry are endeavoring to find ways in which to design a novel PFC circuit to appropriately reduce the on-state loss of the circuit while improving the efficiency of the adapter.